CS 221 - Computer Logic and Organization

Shai Simonson    306 Stanger    (508) 565-1008

Email:  shai@stonehill.edu

Homepage: http://www.stonehill.edu/compsci/shai.htm


Lectures:  MWF 10:30 - 11:20,  Stanger 001

Text:  Digital Logic and Microprocessor Design with VHDL, 5th edition, by Enoch Hwang, Thomson.
           Author's Web Site - Review, Extra practice problems and Solutions.

Exams:  There will be one midterm (20%) and one final examination (30%).

Goals:  To understand the theory and practice of digital electronics that are used to build computers.  You will be build a small prototype of a computer yourself on a "breadboard".

Assignments and Project:  Homeworks and project will be worth 50% of your grade.   You should do these with a partner, and one grade will be given to both people in each group.  You and your partner are responsible for the equipment that you use, and you must return it at the end of the semester exactly as you received it.  Otherwise, if you want to keep the hardware you can pay for it ($175).  It is a good idea for you and your partner to invest in a good pair of wire strippers and a magnifying glass with a light.  Your project kit comes with a manual but you may find the designer's site Yunten Labs to be a useful reference.  You are required to do "project"s 1-5 in the manual, but you can try project 6 for extra credit, if you have succesfully run a program with projects 1-5.  For the project, it is a good idea to show me your progress after each "stage" so that in case anything breaks late in the game, you still get credit for earlier work.  If you wait until the end to show me everything and it doesn't work, I won't be able to tell how much you finished successfully.  

Special Dates:  I will not be in class on Monday, April 21 due to Passover.  You should meet in the room anyway and use the time to work more on your projects.

Reference Links

Cool Circuit Simulator

 Electronic Components and Circuit Diagram - Self Study Simulated Breadboard

Assignments    


Asg1
 Asg2
 Asg3
 Asg4
 Asg5


TakeHome Final Question
Bring in your solution to the final.  You may use your notes and book.  You must work alone.

Design a new control unit for the EC-2 computer described in section 12.3 in your text pages 485-488.  The new control unit should have only 4 states, 0-3,  corresponding to the four levels of the finite state machine on page 485.  You should use two flip flops to represent the state.  You should hand in a finite state machine diagram, next state table, excitation equations, output table, output equations, and final circuit.  Use the techniques of chapter 7 to implement  the finite state machine using Karnaugh maps to minimize equations and circuits.  This alternative design of the finite state machine for EC-2 is like the one we did for the machine I described in class.

Hints and comments:  Because of the fewer number of states, the output equations will depend not only on the current state but also on the opcode, i.e., a Mealy machine.  The output chart on page 487(e) will only have four rows for the four states labeled 00, 01, 10, and 11.  Also, the output chart will have fewer constant 0's and 1's and more entries like (IR5 IR6' IR7 + IR5 IR6 IR7').  By the way, the entry (IR5 IR6' IR7 + IR5 IR6 IR7') is the actual value that you should have in column labeled JMPmux and row labeled state 11.  It means that whenever the instruction is Jz (101) or Jpos (110), the input to the PC comes from the IR rather the incrementing unit, see page 483. 

Note that the PCload signal is controlled by the AC=0 and AC>0 signals, so JMPMux only controls the source of the input to the PC but not whether that input is actually loaded.  If a branch is not taken, PCload would be 0, the PC would continue to hold its normal incremented value, and the JMPMux value is irrelevant.

Brief Syllabus

Week

Topics

 Reading
1 Introduction - How to Build a Computer:   Theory, Number Representation, Gates, Circuits, VHDL.
Chapter 1
2 Boolean Algebra, Sums of Prodcuts, Products of Sums, Karnaugh Maps.
 Chapters 2-3
3-4
 Combinational Circuits: Decoders, Encoders, Multiplexors, Comparaters, Shifters, Arithmetic and Logic Unit.
 Chapter 4
5
 Project Buliding Orientation: Basic Electronics, Breadboards, Voltmeters, Wires, LEDs, Resistors, Power Supplies.
 Yunten Notes
6
 ROMs and PLA's:  General Combinational Circuit Synthesis
Basic Sequential Circuits:  Clocks and Latches, Timing Diagrams.
 Sections 5.6-5.7
Chapter 6
7
 Basic Sequential Circuits:  Latches and Flip-flops:  SR, D, JK, T flip flops, Frequency Dividers.
 Chapter 6
8
 More Sequential Circuits:  Finite State Machines (Mealy and Moore machines) as Control Circuits. Chapter 7
9
 Midterm Examination: Monday, March 17.
10
 More Sequential Circuits:  Memory - Registers, Counters, RAM, ROM.
 Chapter 8
11
 (Optional - If Time Allows) 
Special Puprose Microprocessors:  Dedicated Data Paths, Dedicated Control Units. 
Chapters 9-11
12
 Simple General Purpose Microprocessors:   Machine Language, Data Path, Control Unit - FSM's Revisited.
How to Build a Computer - Putting it All Together.
 Chapter 12
Various 4-15
 Project Building:   Manual Design of a Simple Computer: ALU, Registers, RAM, Bus, I/O, Interrupts.
 Yunten Notes