Lectures: MWF 10:30 - 11:20, 001 Stanger
Exams: There will be one midterm (25%) and one final examination (35%).
Assignments: Homeworks will be worth 40% of your
grade.
You may (but are not required to) do these with a partner, and one
grade
will be given to both people in each group. All programs should
be written using SPIM, a simulator for the MIPS architecture. You
can download
your own copy of SPIM for whatever computer you own. PCSpim, the
version for PCs, should already
be loaded on the machines in the lab. Make sure the settings are
set as below:

You should email your assignments to cs303@stonehill.edu, and not to my personal email. Please send each program and problem set as a separate text file attachment, and Zip them all into one directory with your nameon it. For problem sets, please type or scan and include as a separate file.
Course Description: What
goes on behind the scenes after
you compile your program? Students learn how a computer is put
together,
and the relationship between the hardware and the instruction
sets.
We study the MIPS machine language and the high level organization of a
fully
pipelined
modern RISC machine: including:
ALU
design, CPU design, pipelining, memory organization, cache and virtual
memory, I/O, and methods of measuring the successfulness of these
features.
Special Dates: Due to Jewish holidays, I will not be in
class on September 14 and 28, and October 5. I will announce in
class what alternative arrangements
I will make for these days.
Reference
Links
Wikimedia
Review for MIPS Download PCSpim
SPIM
Quick Reference
Sample
Programs
Week |
Topics |
Reading
|
| 1 | Overview. Assembly
Language. Building a Simple Computer. Measuring
Performance.
CISC versus RISC. |
Chapters 1, 4, Online |
| 2-4 | Instruction Sets and Data
Representation - Two's complement, Sign Magnitude, Floating
Point, ASCII.
Using the SPIM Simulator - Data and Directives, Arithmetic and Memory Operations, Control Structures, Arrays. |
Chapters 2, 3 |
| 5-6 | Registers and Address Modes. Data
Structures,
Procedures, Activation Records, Parameter Passing, Stacks. |
Chapter 2, Appendix A |
| 7 |
Machine Language and MIPS
Instruction Formats. Assemblers - One and Two Pass. |
Chapter 2, Appendix A |
| 8 |
Midterm Examination Exceptions |
October 26 Appendix B |
| 9-10 |
Data Path and
Control
Architecture - Single versus Multi-cycle. Hardwired
vs. Microprogramming. |
Chapter 5, Appendix C |
| 11-12 | Pipelining - An Efficient CPU, Performance Measures and Hazard Handling. Implementation. | Chapter 6 |
| 12-13 | Memory Architecture - Hierarchical Structures: Cache and Virtual Memory. | Chapter 7 |
| 14 | I/O Architecture - Design and Performance. | Chapter 8 |
| 15 | Review |